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5-Lane 5-Port PCI Express(R) Switch
(R)
89PES5T5 Data Sheet
Advance Information*
Device Overview
The 89HPES5T5 is a member of IDT's PRECISETM family of PCI Express switching solutions. The PES5T5 is an 5-lane, 5-port peripheral chip that performs PCI Express Base switching. It provides connectivity and switching functions between a PCI Express upstream port and up to four downstream ports and supports switching between downstream ports.
Features
High Performance PCI Express Switch - Five 2.5Gbps PCI Express lanes - Five switch ports - Upstream port is x1 - Downstream ports are x1 - Low-latency cut-through switch architecture - Support for Max Payload Sizes up to 256 bytes - One virtual channel - Eight traffic classes - PCI Express Base Specification Revision 1.1 compliant Flexible Architecture with Numerous Configuration Options - Automatic lane reversal on all ports - Automatic polarity inversion - Ability to load device configuration from serial EEPROM Legacy Support - PCI compatible INTx emulation - Bus locking
Highly Integrated Solution - Requires no external components - Incorporates on-chip internal memory for packet buffering and queueing - Integrates five 2.5 Gbps embedded SerDes with 8B/10B encoder/decoder (no separate transceivers needed) Reliability, Availability, and Serviceability (RAS) Features - Internal end-to-end parity protection on all TLPs ensures data integrity even in systems that do not implement end-to-end CRC (ECRC) - Supports ECRC and Advanced Error Reporting - Supports PCI Express Native Hot-Plug, Hot-Swap capable I/O - Compatible with Hot-Plug I/O expanders used on PC motherboards Power Management - Utilizes advanced low-power design techniques to achieve low typical power consumption - Supports PCI Power Management Interface specification (PCIPM 1.2) - Unused SerDes are disabled. - Supports Advanced Configuration and Power Interface Specification, Revision 2.0 (ACPI) supporting active link state Testability and Debug Features - Built in Pseudo-Random Bit Stream (PRBS) generator - Numerous SerDes test modes - Ability to read and write any internal register via the SMBus - Ability to bypass link training and force any link into any mode - Provides statistics and performance counters
Block Diagram
5-Port Switch Core / 5 PCI Express Lanes
Frame Buffer Route Table Port Arbitration Scheduler
Transaction Layer Data Link Layer
Transaction Layer Data Link Layer
Transaction Layer Data Link Layer
Transaction Layer Data Link Layer
Transaction Layer Data Link Layer
Mux / Demux
Phy Logical Layer
Mux / Demux
Phy Logical Layer
Mux / Demux
Phy Logical Layer
Mux / Demux
Phy Logical Layer
Mux / Demux
Phy Logical Layer
SerDes
SerDes
SerDes
SerDes
SerDes
(Port 0)
(Port 2)
(Port 3)
Figure 1 Internal Block Diagram
(Port 4)
(Port 5)
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.
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(c) 2007 Integrated Device Technology, Inc. *Notice: The information in this document is subject to change without notice
September 7, 2007
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IDT 89PES5T5 Data Sheet
11 General Purpose Input/Output Pins - Each pin may be individually configured as an input or output - Each pin may be individually configured as an interrupt input - Some pins have selectable alternate functions Packaged in a 15mm x 15mm 196-ball BGA with 1mm ball spacing
Product Description Utilizing standard PCI Express interconnect, the PES5T5 provides the most efficient I/O connectivity solution for applications requiring high throughput, low latency, and simple board layout with a minimum number of board layers. It provides 2.5 GBps (20 Gbps) of aggregated, full-duplex switching capacity through 5 integrated serial lanes, using proven and robust IDT technology. Each lane provides 2.5 Gbps of bandwidth in both directions and is fully compliant with PCI Express Base specification revision 1.1. The PES5T5 is based on a flexible and efficient layered architecture. The PCI Express layer consists of SerDes, Physical, Data Link and Transaction layers in compliance with PCI Express Base specification Revision 1.1. The PES5T5 can operate either as a store and forward or cut-through switch and is designed to switch memory and I/O transactions. It supports eight Traffic Classes (TCs) and one Virtual Channel (VC) with sophisticated resource management to allow efficient switching for applications requiring additional narrow port connectivity.
North Bridge
Memory Memory Memory Memory
South Bridge
x1
PES5T5
x1
GE LOM
x1
GE LOM
x1
GE
x1
1394
Figure 2 I/O Expansion Application
SMBus Interface The PES5T5 contains two SMBus interfaces. The slave interface provides full access to the configuration registers in the PES5T5, allowing every configuration register in the device to be read or written by an external agent. The master interface allows the default configuration register values of the PES5T5 to be overridden following a reset with values programmed in an external serial EEPROM. The master interface is also used by an external Hot-Plug I/O expander. Six pins make up each of the two SMBus interfaces. These pins consist of an SMBus clock pin, an SMBus data pin, and 4 SMBus address pins. In the slave interface, these address pins allow the SMBus address to which the device responds to be configured. In the master interface, these address pins allow the SMBus address of the serial configuration EEPROM from which data is loaded to be configured. The SMBus address is set up on negation of PERSTN by sampling the corresponding address pins. When the pins are sampled, the resulting address is assigned as shown in Table 1.
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Processor
Processor
IDT 89PES5T5 Data Sheet
Bit 1 2 3 4 5 6 7
Slave SMBus Address SSMBADDR[1] SSMBADDR[2] SSMBADDR[3] 0 SSMBADDR[5] 1 1
Master SMBus Address MSMBADDR[1] MSMBADDR[2] MSMBADDR[3] MSMBADDR[4] 1 0 1
Table 1 Master and Slave SMBus Address Assignment
In the split configuration, the master and slave SMBuses operate as two independent buses and thus multi-master arbitration is never required. The PES5T5 supports reading and writing of the serial EEPROM on the master SMBus via the slave SMBus, allowing in system programming of the serial EEPROM.
PES5T5
Processor SMBus Master
Serial EEPROM
...
Other SMBus Devices
PES5T5
Processor SMBus Master
...
Other SMBus Devices
SSMBCLK SSMBDAT MSMBCLK MSMBDAT
SSMBCLK SSMBDAT MSMBCLK MSMBDAT
Serial EEPROM
(a) Unified Configuration and Management Bus
(b) Split Configuration and Management Buses
Figure 3 SMBus Interface Configuration Examples
Hot-Plug Interface The PES5T5 supports PCI Express Hot-Plug on each downstream port. To reduce the number of pins required on the device, the PES5T5 utilizes an external I/O expander, such as that used on PC motherboards, connected to the SMBus master interface. Following reset and configuration, whenever the state of a Hot-Plug output needs to be modified, the PES5T5 generates an SMBus transaction to the I/O expander with the new value of all of the outputs. Whenever a Hot-Plug input changes, the I/O expander generates an interrupt which is received on the IOEXPINTN input pin (alternate function of GPIO) of the PES5T5. In response to an I/O expander interrupt, the PES5T5 generates an SMBus transaction to read the state of all of the Hot-Plug inputs from the I/O expander.
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As shown in Figure 3, the master and slave SMBuses may be used in a unified or split configuration. In the unified configuration, shown in Figure 3(a), the master and slave SMBuses are tied together and the PES5T5 acts both as a SMBus master as well as a SMBus slave on this bus. This requires that the SMBus master or processor that has access to PES5T5 registers supports SMBus arbitration. In some systems, this SMBus master interface may be implemented using general purpose I/O pins on a processor or micro controller, and may not support SMBus arbitration. To support these systems, the PES5T5 may be configured to operate in a split configuration as shown in Figure 3(b).
IDT 89PES5T5 Data Sheet
General Purpose Input/Output The PES5T5 provides 11 General Purpose Input/Output (GPIO) pins that may be used by the system designer as bit I/O ports. Each GPIO pin may be configured independently as an input or output through software control. Some GPIO pins are shared with other on-chip functions. These alternate functions may be enabled via software, SMBus slave interface, or serial configuration EEPROM.
Pin Description
The following tables lists the functions of the pins provided on the PES5T5. Some of the functions listed may be multiplexed onto the same pin. The active polarity of a signal is defined using a suffix. Signals ending with an "N" are defined as being active, or asserted, when at a logic zero (low) level. All other signals (including clocks, buses, and select lines) will be interpreted as being active, or asserted, when at a logic one (high) level.
Signal PE0RP[0] PE0RN[0] PE0TP[0] PE0TN[0] PE2RP[0] PE2RN[0] PE2TP[0] PE2TN[0] PE3RP[0] PE3RN[0] PE3TP[0] PE3TN[0] PE4RP[0] PE4RN[0] PE4TP[0] PE4TN[0] PE5RP[0] PE5RN[0] PE5TP[0] PE5TN[0] PEREFCLKP PEREFCLKN
Type I O I O I O I O I O I
Name/Description PCI Express Port 0 Serial Data Receive. Differential PCI Express receive pair for port 0. PCI Express Port 0 Serial Data Transmit. Differential PCI Express transmit pair for port 0.
PCI Express Port 2 Serial Data Transmit. Differential PCI Express transmit pair for port 2. PCI Express Port 3 Serial Data Receive. Differential PCI Express receive pair for port 3. PCI Express Port 3 Serial Data Transmit. Differential PCI Express transmit pair for port 3. PCI Express Port 4 Serial Data Receive. Differential PCI Express receive pair for port 4. PCI Express Port 4 Serial Data Transmit. Differential PCI Express transmit pair for port 4. PCI Express Port 5 Serial Data Receive. Differential PCI Express receive pair for port 5. PCI Express Port 5 Serial Data Transmit. Differential PCI Express transmit pair for port 5. PCI Express Reference Clock. Differential reference clock pair input. This clock is used as the reference clock by on-chip PLLs to generate the clocks required for the system logic and on-chip SerDes. The frequency of the differential reference clock is determined by the REFCLKM signal. PCI Express Reference Clock Mode Select. This signal selects the frequency of the reference clock input. 0x0 - 100 MHz 0x1 - 125 MHz Table 2 PCI Express Interface Pins
REFCLKM
I
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PCI Express Port 2 Serial Data Receive. Differential PCI Express receive pair for port 2.
IDT 89PES5T5 Data Sheet
Signal MSMBADDR[4:1] MSMBCLK MSMBDAT SSMBADDR[5,3:1] SSMBCLK SSMBDAT
Type I I/O I/O I I/O I/O
Name/Description Master SMBus Address. These pins determine the SMBus address of the serial EEPROM from which configuration information is loaded. Master SMBus Clock. This bidirectional signal is used to synchronize transfers on the master SMBus. Master SMBus Data. This bidirectional signal is used for data on the master SMBus. Slave SMBus Address. These pins determine the SMBus address to which the slave SMBus interface responds. Slave SMBus Clock. This bidirectional signal is used to synchronize transfers on the slave SMBus. Slave SMBus Data. This bidirectional signal is used for data on the slave SMBus. Table 3 SMBus Interface Pins
Signal GPIO[0]
Type I/O
Name/Description General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: P2RSTN Alternate function pin type: Output Alternate function: Reset output for downstream port 2 General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: P4RSTN Alternate function pin type: Output Alternate function: Reset output for downstream port 4 General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: IOEXPINTN0 Alternate function pin type: Input Alternate function: I/O Expander interrupt 0 input General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: IOEXPINTN1 Alternate function pin type: Input Alternate function: I/O Expander interrupt 1 input General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: IOEXPINTN2 Alternate function pin type: Input Alternate function: I/O Expander interrupt 2 input General Purpose I/O. This pin can be configured as a general purpose I/O pin. General Purpose I/O. This pin can be configured as a general purpose I/O pin.
GPIO[1]
I/O
GPIO[2]
I/O
GPIO[3]
I/O
GPIO[4]
I/O
GPIO[5] GPIO[6]
I/O I/O
Table 4 General Purpose I/O Pins (Part 1 of 2)
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IDT 89PES5T5 Data Sheet Signal GPIO[7] Type I/O Name/Description General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: GPEN Alternate function pin type: Output Alternate function: General Purpose Event (GPE) output General Purpose I/O. This pin can be configured as a general purpose I/O pin. General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: P3RSTN Alternate function pin type: Output Alternate function: Reset output for downstream port 3 General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: P5RSTN Alternate function pin type: Output Alternate function: Reset output for downstream port 5 Table 4 General Purpose I/O Pins (Part 2 of 2)
GPIO[8] GPIO[9]
I/O I/O
GPIO[10]
I/O
Signal APWRDISN CCLKDS
Type I I
Name/Description Auxiliary Power Disable Input. When this pin is active, it disables the device from using auxiliary power supply. Common Clock Downstream. The assertion of this pin indicates that all downstream ports are using the same clock source as that provided to downstream devices.This bit is used as the initial value of the Slot Clock Configuration bit in all of the Link Status Registers for downstream ports. The value may be override by modifying the SCLK bit in the downstream port's PCIELSTS register. Common Clock Upstream. The assertion of this pin indicates that the upstream port is using the same clock source as the upstream device. This bit is used as the initial value of the Slot Clock Configuration bit in the Link Status Register for the upstream port. The value may be overridden by modifying the SCLK bit in the PA_PCIELSTS register. Master SMBus Slow Mode. The assertion of this pin indicates that the master SMBus should operate at 100 KHz instead of 400 kHz. This value may not be overridden. Fundamental Reset. Assertion of this signal resets all logic inside the PES5T5 and initiates a PCI Express fundamental reset. Table 5 System Pins (Part 1 of 2)
CCLKUS
I
MSMBSMODE
I
PERSTN
I
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IDT 89PES5T5 Data Sheet Signal RSTHALT Type I Name/Description Reset Halt. When this signal is asserted during a PCI Express fundamental reset, the PES5T5 executes the reset procedure and remains in a reset state with the Master and Slave SMBuses active. This allows software to read and write registers internal to the device before normal device operation begins. The device exits the reset state when the RSTHALT bit is cleared in the PA_SWCTL register by an SMBus master. Switch Mode. These configuration pins determine the PES5T5 switch operating mode. 0x0 - Normal switch mode 0x1 - Normal switch mode with Serial EEPROM initialization 0x2 - through 0xF Reserved Wake Input/Output. The WAKEN signal is an input or output. The WAKEN signal input/output selection can be made through the WAKEDIR bit setting in the WAKEUPCNTL register. Table 5 System Pins (Part 2 of 2)
SWMODE[2:0]
I
WAKEN
I/O
Signal JTAG_TCK
Type I
Name/Description JTAG Clock. This is an input test clock used to clock the shifting of data into or out of the boundary scan logic or JTAG Controller. JTAG_TCK is independent of the system clock with a nominal 50% duty cycle. JTAG Data Input. This is the serial data input to the boundary scan logic or JTAG Controller. JTAG Data Output. This is the serial data shifted out from the boundary scan logic or JTAG Controller. When no data is being shifted out, this signal is tri-stated. JTAG Mode. The value on this signal controls the test mode select of the boundary scan logic or JTAG Controller. JTAG Reset. This active low signal asynchronously resets the boundary scan logic and JTAG TAP Controller. An external pull-up on the board is recommended to meet the JTAG specification in cases where the tester can access this signal. However, for systems running in functional mode, one of the following should occur: 1) actively drive this signal low with control logic 2) statically drive this signal low with an external pull-down on the board Table 6 Test Pins
JTAG_TDI JTAG_TDO
I O
JTAG_TMS JTAG_TRST_N
I I
Signal VDDCORE VDDIO VDDPE VDDAPE VTTPE VSS
Type I I I I I I
Name/Description Core VDD. Power supply for core logic. I/O VDD. LVTTL I/O buffer power supply. PCI Express Digital Power. PCI Express digital power used by the digital power of the SerDes. PCI Express Analog Power. PCI Express analog power used by the PLL and bias generator. PCI Express Termination Power. Ground. Table 7 Power and Ground Pins
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IDT 89PES5T5 Data Sheet
Pin Characteristics
Note: Some input pads of the PES5T5 do not contain internal pull-ups or pull-downs. Unused inputs should be tied off to appropriate levels. This is especially critical for unused control signal inputs which, if left floating, could adversely affect operation. Also, any input pin left floating can cause a slight increase in power consumption.
Function PCI Express Interface
Pin Name PE0RN[0] PE0RP[0] PE0TN[0] PE0TP[0] PE2RN[0] PE2RP[0] PE2TN[0] PE2TP[0] PE3RN[0] PE3RP[0] PE3TN[0] PE3TP[0] PE4RN[0] PE4RP[0] PE4TN[0] PE4TP[0] PE5RN[0] PE5RP[0] PE5TN[0] PE5TP[0] PEREFCLKN PEREFCLKP REFCLKM
Type I I O O I I O O I I O O I I O O I I O O I I I I I/O I/O I I/O I/O I/O
Buffer CML
I/O Type Serial Link
Internal Resistor
Notes
LVPECL/ CML LVTTL LVTTL
Diff. Clock Input Input Input STI1 STI Input STI STI pull-up pull-down pull-up
Refer toTable 9
SMBus
MSMBADDR[4:1] MSMBCLK MSMBDAT SSMBADDR[5,3:1] SSMBCLK SSMBDAT
General Purpose I/O
GPIO[10:0]
LVTTL
High Drive
pull-up
Table 8 Pin Characteristics (Part 1 of 2)
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IDT 89PES5T5 Data Sheet Function System Pins Pin Name APWRDISN CCLKDS CCLKUS MSMBSMODE PERSTN RSTHALT SWMODE[2:0] WAKEN EJTAG / JTAG JTAG_TCK JTAG_TDI JTAG_TDO JTAG_TMS JTAG_TRST_N
1.
Type I I I I I I I I/O I I O I I
Buffer LVTTL
I/O Type Input
Internal Resistor pull-down pull-up pull-up pull-down pull-down pull-down open-drain
Notes
LVTTL
STI STI STI STI
pull-up pull-up pull-up pull-up
Schmitt Trigger Input (STI).
Table 8 Pin Characteristics (Part 2 of 2)
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IDT 89PES5T5 Data Sheet
Logic Diagram -- PES5T5
PEREFCLKP PEREFCLKN REFCLKM PE0TP[0] PE0TN[0]
Reference Clock PCI Express Switch SerDes Input Port 0 PCI Express Switch SerDes Input Port 2
PCI Express Switch SerDes Output Port 0
PE0RP[0] PE0RN[0] PE2TP[0] PE2TN[0]
PCI Express Switch SerDes Output Port 2
PE2RP[0] PE2RN[0] PE3TP[0] PE3TN[0]
PCI Express Switch SerDes Output Port 3
PCI Express Switch SerDes Input Port 3
PE3RP[0] PE3RN[0]
PE4TP[0]
PE5TP[0] PE5TN[0]
PCI Express Switch SerDes Output Port 5
PCI Express Switch SerDes Input Port 5
PE5RP[0] PE5RN[0]
11
GPIO[10:0]
General Purpose I/O
Master SMBus Interface
MSMBADDR[4:1] MSMBCLK MSMBDAT SSMBADDR[5,3:1] SSMBCLK SSMBDAT
4
JTAG_TCK JTAG_TDI JTAG_TDO JTAG_TMS
JTAG Pins
4
JTAG_TRST_N VDDCORE VDDIO VDDPE VDDAPE VSS VTTPE
Slave SMBus Interface
MSMBSMODE
Power/Ground
System Pins
CCLKDS CCLKUS RSTHALT PERSTN SWMODE[2:0] WAKEN APWRDISN
3
Figure 4 PES5T5 Logic Diagram
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PCI Express Switch SerDes Input Port 4
PES5T5
PE4RP[0] PE4RN[0]
PE4TN[0]
PCI Express Switch SerDes Output Port 4
IDT 89PES5T5 Data Sheet
System Clock Parameters
Values based on systems running at recommended supply voltages and operating temperatures, as shown in Tables 13 and 14.
Parameter PEREFCLK RefclkFREQ RefclkDC2 TR, TF VSW Tjitter
1. The input clock 2. 3.
Description
Min
Typical
Max 1251
Unit
Input reference clock frequency range Duty cycle of input clock Rise/Fall time of input clocks Differential input voltage swing4 Input clock jitter (cycle-to-cycle)
100 40 0.6 50
MHz % RCUI3 V ps
60 0.2*RCUI 1.6 125
Table 9 Input Clock Requirements
frequency will be either 100 or 125 MHz depending on signal REFCLKM. ClkIn must be AC coupled. Use 0.01 -- 0.1 F ceramic capacitors. RCUI (Reference Clock Unit Interval) refers to the reference clock period. coupling required.
AC Timing Characteristics
Parameter PCIe Transmit TTX-RISE, TTX-FALL UI TTX-MAX-JITTER TTX-EYE TTX-EYE-MEDIAN-toMAX-JITTER
Description
Min
Typical
Max 1101
Units
Rise / Fall time of TxP, TxN outputs Unit Interval Transmitter Total Jitter (peak-to-peak) Minimum Tx Eye Width (1 - TTX-MAX-JITTER) Maximum time between the jitter median and maximum deviation from the median Transmitter data latency (for n=10) Transmitter data latency (for n=20) Transmitter data skew between any 2 lanes Maximum time to transition to a valid electrical idle after sending an Electrical Idle ordered set Time to exit Electrical Idle (L0s) state into L0 Time from asserting Beacon TxEn to beacon being transmitted on the lane Pulse width of RxDetectEn input RxDetectEn falling edge to RxDetect delay Recover data latency for n=10 Recover data latency for n=20
80 399.88 0.75 400
ps ps UI UI UI bits bits ps ns ns ns ns ns bits bits
400.12 0.252 0.15
LTLAT-10 LTLAT-20 TTX-SKEW TTX-IDLE-SET-TOIDLE
9 9 500 4 12 30 9.8 10 1 28 49
11 11 1300 6 16 80 10.2 2 29 60
TEIExit TBTEn TRxDetectEn TRxDetect PCIe Receive LRLAT-10 LRLAT-20
Table 10 PCIe AC Timing Characteristics (Part 1 of 2)
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4. AC
IDT 89PES5T5 Data Sheet Parameter TRX-SKEW TBDDly TRX-IDLE_ENTER TRX-IDLE_EXIT TRX-MAX-JITTER TRX-EYE TRX-EYE-MEDIAN-toMAX JITTER
1. As 2. 3.
Description Receiver data skew between any 2 lanes Beacon-Activity on channel to detection of Beacon
3
Min
Typical
Max 20 200
Units ns s ns ns UI UI UI
Delay from detection of Electrical Idle condition on the channel to assertion of TxIdleDetect output Delay from detection of L0s to L0 transition to de-assertion of TxIdleDetect output Receiver total jitter tolerance Minimum Receiver Eye Width Maximum time between jitter median and max deviation from median Table 10 PCIe AC Timing Characteristics (Part 2 of 2) 0.35
10 5
20 10 0.65 0.325
measured between 20% and 80% points. Will depend on package characteristics.
Measured using PCI Express Compliance Pattern. This is a function of beacon frequency.
Signal GPIO GPIO[10:0]1
1. 2.
Symbol
Reference Min Max Unit Edge
Timing Diagram Reference
Tpw_13b2
None
50
--
ns
See Figure 5.
Table 11 GPIO AC Timing Characteristics
GPIO signals must meet the setup and hold times if they are synchronous or the minimum pulse width if they are asynchronous. The values for this symbol were determined by calculation, not by testing.
EXTCLK Tdo_13a GPIO (synchronous output) Tpw_13b GPIO (asynchronous input) Tdo_13a
Figure 5 GPIO AC Timing Waveform
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IDT 89PES5T5 Data Sheet
Signal JTAG JTAG_TCK
Symbol
Reference Edge
Min
Max
Unit
Timing Diagram Reference
Tper_16a Thigh_16a, Tlow_16a
none
25.0 10.0
50.0 25.0 -- -- 11.3 11.3 --
ns ns ns ns ns ns ns
See Figure 6.
JTAG_TMS1, JTAG_TDI JTAG_TDO JTAG_TRST_N
1.
Tsu_16b Thld_16b Tdo_16c Tdz_16c2 Tpw_16d2
JTAG_TCK rising JTAG_TCK falling none
2.4 1.0 -- -- 25.0
Table 12 JTAG AC Timing Characteristics
2.
The values for this symbol were determined by calculation, not by testing.
Tlow_16a Thigh_16a JTAG_TCK Thld_16b Tsu_16b JTAG_TDI Thld_16b Tsu_16b JTAG_TMS Tdo_16c JTAG_TDO Tpw_16d JTAG_TRST_N Figure 6 JTAG AC Timing Waveform Tdz_16c Tper_16a
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The JTAG specification, IEEE 1149.1, recommends that JTAG_TMS should be held at 1 while the signal applied at JTAG_TRST_N changes from 0 to 1. Otherwise, a race may occur if JTAG_TRST_N is deasserted (going from low to high) on a rising edge of JTAG_TCK when JTAG_TMS is low, because the TAP controller might go to either the Run-Test/Idle state or stay in the Test-Logic-Reset state.
IDT 89PES5T5 Data Sheet
Recommended Operating Supply Voltages
Symbol VDDCORE VDDI/O VDDPE VDDAPE VTTPE VSS Parameter Internal logic supply I/O supply except for SerDes LVPECL/CML PCI Express Digital Power PCI Express Analog Power PCI Express Serial Data Transmit Termination Voltage Common ground Minimum 0.9 3.135 0.9 0.9 1.425 0 Table 13 PES5T5 Operating Voltages Typical 1.0 3.3 1.0 1.0 1.5 0 Maximum 1.1 3.465 1.1 1.1 1.575 0 Unit V V V V V V
Power-Up/Power-Down Sequence
When powering up, each voltage level must ramp and stabilize prior to applying the next voltage in the sequence to ensure internal latch-up issues are avoided. There are no maximum time limitations in ramping to valid power levels. The power-down sequence must be in the reverse order of the power-up sequence.
Recommended Operating Temperature
Grade Commercial Temperature 0C to +70C Ambient Table 14 PES5T5 Operating Temperatures
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This section describes the sequence in which various voltages must be applied to the part during power-up to ensure proper functionality. For the PES5T5, the power-up sequence must be as follows: 1. VDDI/O -- 3.3V 2. VDDCore, VDDPE, VDDAPE -- 1.0V 3. VTTPE -- 1.5V
IDT 89PES5T5 Data Sheet
Power Consumption
Parameter IDDI/O Typ. tbd Max. tbd Unit mA Conditions Tambient = 25oC Max. values use the maximum voltages listed in Table 13. Typical values use the typical voltages listed in that table.
IDDCore IDDPE, IDD APE ITTPE Power Dissipation
Normal mode Standby mode1
tbd tbd tbd tbd tbd
tbd -- tbd tbd tbd tbd --
mA mA mA mA mA W W
Normal mode Standby mode
1
tbd tbd
1.
All ports in D1 state.
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Table 15 PES5T5 Power Consumption
IDT 89PES5T5 Data Sheet
DC Electrical Characteristics
Values based on systems running at recommended supply voltages, as shown in Table 13. Note: See Table 8, Pin Characteristics, for a complete I/O listing.
Min1 Typ1 Max1
I/O Type Serial Link
Parameter PCIe Transmit VTX-DIFFp-p VTX-DE-RATIO VTX-DC-CM VTX-CM-ACP VTX-CM-DCactive-idle-delta
Description
Unit
Conditions
Differential peak-to-peak output voltage De-emphasized differential output voltage DC Common mode voltage RMS AC peak common mode output voltage Abs delta of DC common mode voltage between L0 and idle Abs delta of DC common mode voltage between D+ and DElectrical idle diff peak output Voltage change during receiver detection Transmitter Differential Return loss Transmitter Common Mode Return loss DC Differential TX impedance Single ended TX Impedance TX Eye Height (De-emphasized bits) TX Eye Height (Transition bits)
800 -3 -0.1 1
1200 -4 3.7 20 100 25 20 600
mV dB V mV mV mV mV mV dB dB
delta
VTX-Idle-DiffP VTX-RCV-Detect RLTX-DIFF RLTX-CM ZTX-DEFF-DC ZOSE Transmitter Eye Diagram Transmitter Eye Diagram PCIe Receive VRX-DIFFp-p VRX-CM-AC RLRX-DIFF RLRX-CM ZRX-DIFF-DC ZRX-COMM-DC
12 6 80 40 505 800 100 50 650 950 120 60
mV mV
Differential input voltage (peak-to-peak) Receiver common-mode voltage for AC coupling Receiver Differential Return Loss Receiver Common Mode Return Loss Differential input impedance (DC) Single-ended input impedance
175
1200 150
mV mV dB dB
15 6 80 40 200k 65 100 50 350k 175 120 60
mV
ZRX-COMM-HIGH- Powered down input common mode impedance (DC) Z-DC VRX-IDLE-DETDIFFp-p
Electrical idle detect threshold
PCIe REFCLK CIN Input Capacitance 1.5 -- pF
Table 16 DC Electrical Characteristics (Part 1 of 2)
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VTX-CM-DC-line-
IDT 89PES5T5 Data Sheet I/O Type Other I/Os LOW Drive Output High Drive Output Schmitt Trigger Input (STI) Input IOL IOH IOL IOH VIL VIH VIL VIH Capacitance Leakage CIN Inputs I/OLEAK W/O Pull-ups/downs I/OLEAK WITH Pull-ups/downs
1.
Parameter
Description
Min1
Typ1
Max1
Unit
Conditions
-- -- -- -- -0.3 2.0 -0.3 2.0 -- -- -- --
2.5 -5.5 12.0 -20.0 -- -- -- -- -- -- -- --
-- -- -- -- 0.8 VDDIO + 0.5 0.8 VDDIO + 0.5 8.5 + 10 + 10 + 80
mA mA mA mA V V V V pF
VOL = 0.4v VOH = 1.5V VOL = 0.4v VOH = 1.5V -- -- -- -- -- VDDI/O (max) VDDI/O (max) VDDI/O (max)
A A A
Table 16 DC Electrical Characteristics (Part 2 of 2)
Minimum, Typical, and Maximum values meet the requirements under PCI Specification 1.1.
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IDT 89PES5T5 Data Sheet
Package Pinout -- 196-BGA Signal Pinout for PES5T5
The following table lists the pin numbers and signal names for the PES5T5 device.
Pin A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 C1 C2 C3 C4 C5 C6 VSS NC VSS NC NC VSS NC NC VSS NC PE0TN00 VSS PE0RP00 VSS VSS NC VSS NC NC VSS NC NC VSS NC PE0TP00 VSS PE0RN00 VSS WAKEN APWRDISN CCLKUS VSS VSS VTTPE Function Alt Pin C7 C8 C9 C10 C11 C12 C13 C14 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 Function VDDAPE VDDAPE VTTPE CCLKDS VSS VDDIO VSS SWMODE_0 SSMBCLK SSMBDAT VSS VDDIO VDDCORE VDDCORE VDDPE VDDPE VDDCORE VDDIO VDDCORE VSS SWMODE_2 SWMODE_1 SSMBADDR_1 SSMBADDR_3 VDDIO VDDCORE VSS VSS VSS VSS VSS VDDCORE VSS VDDIO Alt Pin E13 E14 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 G13 G14 H1 H2 H3 H4 Function VDDCORE VSS MSMBDAT SSMBADDR_2 SSMBADDR_5 VDDIO VSS VDDCORE VDDCORE VSS VDDCORE VDDCORE VDDIO GPIO_00 PERSTN VSS MSMBADDR_4 MSMBCLK VDDIO VSS VDDCORE VSS VSS VDDCORE VSS VSS VSS VDDIO GPIO_01 RSTHALT MSMBADDR_1 MSMBADDR_2 MSMBADDR_3 VDDCORE 1 1 Alt Pin H5 H6 H7 H8 H9 H10 H11 H12 H13 H14 J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 J13 J14 K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 VSS VDDCORE VDDCORE VSS VSS VDDCORE VDDCORE GPIO_05 GPIO_03 GPIO_02 JTAG_TDO JTAG_TRST_N JTAG_TMS VDDCORE VSS VDDCORE VSS VDDCORE VDDCORE VSS VDDIO VDDIO GPIO_06 GPIO_04 JTAG_TDI VDDIO VDDAPE VSS VDDCORE VSS VSS VSS VSS VSS 1 1 Function Alt
Table 17 PES5T5 196-pin Signal Pin-Out (Part 1 of 2)
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1
IDT 89PES5T5 Data Sheet Pin K11 K12 K13 K14 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 Function VDDCORE VSS GPIO_08 GPIO_07 JTAG_TCK VSS VSS VDDIO VDDCORE VDDCORE VDDPE VDDPE VDDCORE VDDCORE VSS 1 Alt Pin L12 L13 L14 M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 M12 VSS GPIO_10 GPIO_09 VSS VDDCORE VDDCORE VSS VDDIO VTTPE VDDAPE VDDAPE VTTPE VDDIO VDDIO REFCLKM 1 1 Function Alt Pin M13 M14 N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 N12 N13 Function MSMBSMODE VSS PEREFCLKN VSS PE2RN00 VSS PE2TP00 PE3TN00 VSS PE3RN00 PE4RP00 VSS PE4TN00 PE5TP00 VSS Alt Pin N14 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 Function PE5RN00 PEREFCLKP VSS PE2RP00 VSS PE2TN00 PE3TP00 VSS PE3RP00 PE4RN00 VSS PE4TP00 PE5TN00 VSS PE5RP00 Alt
Table 17 PES5T5 196-pin Signal Pin-Out (Part 2 of 2)
Alternate Signal Functions
Pin F12 G13 H14 H13 J14 K14 L14 L13 GPIO GPIO_00 GPIO_01 GPIO_02 GPIO_03 GPIO_04 GPIO_07 GPIO_09 GPIO_10 Alternate P2RSTN P4RSTN IOEXPINTN0 IOEXPINTN1 IOEXPINTN2 GPEN P3RSTN P5RSTN
Table 18 PES5T5 Alternate Signal Functions
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IDT 89PES5T5 Data Sheet
Power Pins
VDDCore D5 D6 D9 D11 E4 E10 E13 F6 F7 F9 F10 G5 G8 H4 H6 H7 VDDCore H10 H11 J4 J6 J8 J9 K5 K11 L5 L6 L9 L10 M2 M3 VDDIO C12 D4 D10 E3 E12 F4 F11 G3 G12 J11 J12 K2 L4 M5 M10 M11 Table 19 PES5T5 Power Pins VDDPE D7 D8 L7 L8 VDDAPE C7 C8 K3 M7 M8 VTTPE C6 C9 M6 M9
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IDT 89PES5T5 Data Sheet
Ground Pins
Vss A1 A3 A6 A9 A12 A14 B1 B3 B6 B9 B12 B14 C4 C5 C11 C13 Vss D3 D12 E5 E6 E7 E8 E9 E11 E14 F5 F8 F14 G4 G6 G7 G9 Vss G10 G11 H5 H8 H9 J5 J7 J10 K4 K6 K7 K8 K9 K10 K12 L2 Vss L3 L11 L12 M1 M4 M14 N2 N4 N7 N10 N13 P2 P4 P7 P10 P13
Table 20 PES5T5 Ground Pins
No Connection Pins
Pin A2 A4 A5 A7 A8 A10 Pin B2 B4 B5 B7 B8 B10
Table 21 PES5T5 No Connection Pins
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IDT 89PES5T5 Data Sheet
PES5T5 Pinout -- Top View
1 2 3 4 5 6 7 8 9 10 11 12 13 14
A B C D E F G H J K L M N P
1 2 3 4 5 6 7 8 9 10 11 12 13 14
A B
X
X
C D E F G H J K L
X
X
M N P
VDDCore (Power) VDDI/O (Power)
x
VTTPE (Power) VDDPE (Power) VDDAPE (Power)
Vss (Ground)
Signals
No Connect
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IDT 89PES5T5 Data Sheet
PES5T5 Package Drawing -- 196-Pin BC196/BCG196
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IDT 89PES5T5 Data Sheet
PES5T5 Package Drawing -- Page Two
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IDT 89PES5T5 Data Sheet
Revision History
August 16, 2007: Initial publication of advanced data sheet. September 7, 2007: Added Power-Up/Power Down Sequence.
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IDT 89PES5T5 Data Sheet
Ordering Information
NN Product Family A Operating Voltage AAA Device Family NNAN Product Detail AA Device Revision AA A Legend A = Alpha Character N = Numeric Character
Package Temp Range
Blank BC BCG ZA
Commercial Temperature (0C to +70C Ambient) BC196 196-ball CABGA BCG196 196-ball CABGA, Green ZA revision
5T5
5-lane, 5-port
PES
PCI Express Switch
H 89
1.0V +/- 0.1V Core Voltage Serial Switching Product
Valid Combinations
89HPES5T5ZABC 89HPES5T5ZABCG 196-pin BC196 package, Commercial Temperature 196-pin Green BCG196 package, Commercial Temperature
(R)
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